This application claims priority to Korean Patent Application No. 2005-73629, filed on Aug. 11, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to clock and data recovery, and more particularly to an apparatus and method for clock and data recovery using a clock frequency that is lower than an input data rate.
2. Description of the Related Art
A clock and data recovery (CDR) circuit generates a clock signal synchronized to an input data signal to recover data with the clock signal. Such a CDR circuit is disclosed in U.S. Patent Application Publication No. 2004-0240599. The CDR circuit is widely used in local area networks (LANs), wired or wireless communications, optical communications, disk drives, and so on.
The CDR circuit is a kind of a phase-locked loop (PLL) and generally includes a phase detector, a charge pump, a low-pass filter (LPF), and a voltage-controlled oscillator (VCO). The phase detector generates error signals by detecting a phase difference between the input data signal and the clock signal generated by the VCO. The charge pump generates a voltage control signal based on the error signals. The voltage control signal determines a clock frequency of the clock signal generated by the VCO.
The clock frequency is increased when the voltage control signal is increased, and is decreased when the voltage control signal is decreased. With time, the CDR circuit decreases a phase difference between the input data signal and the clock signal until synchronization is achieved when the clock frequency is substantially equivalent to a frequency of the input data signal. Such synchronization is desired for recovering valid data from the input data signal.
In the conventional CDR circuit, as the frequency of the input data signal is increased, the clock signal frequency also should be increased. However, designing the VCO to generate a clock signal with substantially higher clock frequency is difficult, and power consumption of the CDR circuit is increased for such higher clock frequency.
As a solution to these problems, one CDR circuit is disclosed in U.S. Patent Application Publication No. 2004-0240599 for using a clock signal having a half of the frequency of the input data signal. Another CDR circuit is disclosed in U.S. Patent Application Publication No. 2004-0155687 using a clock signal having a quarter of the frequency of the input data signal.
For example, FIG. 1 is a block diagram of the conventional CDR circuit disclosed in U.S. Patent Application Publication No. 2004-0155687. FIG. 2 is a timing diagram of signals during operation of the CDR circuit of FIG. 1.
Referring to FIGS. 1 and 2, the CDR circuit includes a phase detector 14, a V/I converter 16, a low pass filter 18, and a voltage-controlled oscillator 12. Clock signals CKO, CK45, CK90 and CK1 35 have a period that is four times a period of the input data signal DIN. The input data signal DIN is sampled at every transition of the clock signals.
Because transitions of the clock signals from the VCO are used for sampling the input data signal DIN in the prior art, the clock signals are formed to have up to a quarter of the frequency of the input data signal. However, lowering the clock frequency even further may be desired as data rates are increased with advancement of technology.